The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory device which has a high packaging density and which is advantageous for attaining a fast operation as well as a high S/N (signal-to-noise) ratio.
As illustrated in FIG. 1, a semiconductor memory is constructed by disposing on a chip 1 a memory array AR in which memory cells MC are arranged in the shape of an array, an X decoder (including a driver) 3 which selects the memory cells MC in a row direction, a Y decoder (including a driver) 4 which selects the memory cells MC in a column direction, timing generator circuits 5 and 6, and besides, an address driver etc. The timing generator circuits 5 and 6 produce various internal timing pulses in synchronism with a clock .phi. so as to control various circuit operations. In addition, supply voltages V.sub.CC (for example, 5 volts) and V.sub.SS (0 volt) are fed to the circuits. Usually, a wiring material of low resistivity such as aluminum is used for power source lines for the supply voltages V.sub.CC and V.sub.SS or timing signal lines for various internal timings. On the other hand, the aluminum of the same layer is used within the memory array AR.
In such prior-art semiconductor memory, a reading operation is performed as stated below. When external address signals A.sub.0 -A.sub.3 are received as inputs, the X decoder 3 is started. When a word line X.sub.0, for example, is consequently selected from among a plurality of word lines X.sub.0 -X.sub.3, a select pulse is delivered to the word line X.sub.0, and the memory cells MC connected therewith deliver read signals to corresponding data lines Y.sub.0 -Y.sub.3. Meanwhile, assuming that a select signal from the Y decoder 4 applied through a Y control line 8 turns on a switch SW.sub.0 to select the data line Y.sub.0, the signal read out to the data line Y.sub.0 is delivered to an input/output line I/O through the switch SW.sub.0 and is externally provided as a data output D.sub.0. In a writing operation, a data input D.sub.i is sent to the input/output line I/O, the switch SW.sub.0 and the data line Y.sub.0 by a write enable signal WE, and the data is written into the memory cell MC which is connected at the intersection point between the data line Y.sub.0 and the selected word line X.sub.0.
In such semiconductor memory, however, the power source lines of the supply voltages V.sub.CC, V.sub.SS as well as the lines of the various timing signals and the memory array employ the identical conductor layer, so that they must be formed in regions separate from each other, making it impossible to reduce the area of the chip. For example, in case of encasing the semiconductor memory in a dual in-line package, the shorter side of the chip needs to be suppressed small. In this case, however, the suppression has been limited with the prior art left intact.
In semiconductor memory devices, as the packaging density is increased in order to increase its storage capacity, the capacity of a charge storage portion in each memory cell decreases. In addition, the area of the memory array on a memory chip increases, and the capacitance of a data line, and the length thereof, both increase. Accordingly, it becomes increasingly difficult to attain the features of both fast operation and high S/N ratio.